Typically, a PLL (Phase Locked Loop) circuit includes a phase comparator, a charge pump, a loop filter, and a voltage controlled oscillator (hereinbelow, also referred to as a “VCO”), and these members constitute a loop. The PLL circuit is used as a frequency synthesizer which outputs an oscillation signal having a frequency that is a constant multiple of the frequency of an input oscillation signal. Further, the PLL circuit is capable of recovering a clock embedded in an input digital signal in a CDR (Clock Data Recovery) device.
The PLL circuit operates as described below. When a control voltage value is inputted to the voltage controlled oscillator, an oscillation signal having a frequency corresponding to the control voltage value is outputted from the voltage controlled oscillator. The oscillation signal outputted from the voltage controlled oscillator or a signal obtained by frequency-dividing the oscillation signal, is inputted as a feedback oscillation signal to the phase comparator. Further, another input signal (an oscillation signal or a digital signal) is also inputted to the phase comparator in addition to the feedback oscillation signal. In the phase comparator, a phase difference between the input signal and the feedback oscillation signal is detected, and a phase difference signal indicating the detected phase difference is outputted to the charge pump.
In the charge pump to which the phase difference signal has been inputted, a current flows between the loop filter and the charge pump so that the phase difference indicated by the phase difference signal is reduced. The loop filter includes a capacitive element having a charge storage amount increased or reduced by a charge transfer from the charge pump side (a charging current) or a charge transfer toward the charge pump side (a discharging current) and maintains a charge storage amount corresponding to an output side voltage value of the charge pump. The loop filter outputs a control voltage value corresponding to the charge storage amount to the voltage controlled oscillator. When the control voltage value outputted from the loop filter is inputted to the voltage controlled oscillator, an oscillation signal having a frequency corresponding to the control voltage value is outputted from the voltage controlled oscillator.
In the PLL circuit having the loop as described above, the control voltage value outputted to the voltage controlled oscillator from the loop filter converges to a certain value so that the phase difference detected by the phase comparator is reduced. The voltage controlled oscillator outputs an oscillation signal having a frequency that is a constant multiple of the frequency of the input oscillation signal or a clock embedded in an input digital signal after the clock is recovered.
There are various types of oscillators as the voltage controlled oscillator. Among the various types of oscillators, an LC-VCO includes an inductor and a capacitor, and outputs an oscillation signal having a frequency corresponding to an input control voltage value using a resonance phenomenon by the inductor and the capacitor. As compared to the other types of voltage controlled oscillators, jitter is small in the LC-VCO. Thus, when the frequency is 10 Gbps or more, it is essential to use the LC-VCO among various types of voltage controlled oscillators.
As compared to the other types of voltage controlled oscillators, changes in the frequency of the output oscillation signal in response to changes in the control voltage value are small in the LC-VCO. In the LC-VCO, an FV characteristic which determines the relationship between the frequency (F) of the output oscillation signal and the control voltage value (V) depends on a capacitance value of the capacitor. Further, the range of the control voltage value inputted to the LC-VCO is limited. When the control voltage value falls outside the range, a proportional relationship in frequency between input and output is not satisfied.
The frequency of a transferred signal may vary with time by spread spectrum (hereinbelow, referred to as “SS”). When the frequency of a signal is constant, an energy of an electromagnetic wave radiated from the signal is concentrated on the frequency. Thus, there is a problem of electro magnetic interference (hereinbelow, referred to as “EMI”). On the other hand, when the frequency of a signal is intentionally modulated by SS, an energy of an electromagnetic wave radiated from the signal has an expanded frequency band and a small peak. The problem of EMI can be reduced by SS. When the bit rate of a signal is high or a transfer distance of a signal is long, it is desired to modulate the frequency of the signal by SS. The degree of modulation of frequency by SS may require ±1.0% or more.
For example, a serializer device which converts parallel data to serial data latches the parallel data at the timing designated by a first clock having a low frequency and outputs the serial data at the timing designated by a second clock having a high frequency. In such a serializer device, SS may be applied to the output serial data. In this case, a PLL circuit used in the serializer device takes in a first clock to which SS is applied, generates a second clock having a frequency that is a constant multiple of the frequency of the first clock and to which SS is applied, and outputs the generated second clock.
When the bit rate of serial data is high and the frequency of the second clock is high, as described above, an LC-VCO is preferably used as a voltage controlled oscillator included in the PLL circuit. However, when the modulation of frequency by SS in the first clock inputted to the PLL circuit is large, variations in a control voltage value inputted to the LC-VCO also become large. Under such a condition, the frequency of the second clock outputted from the PLL circuit is not in proportion to the frequency of the first clock. In order to avoid such a situation, it is important to appropriately set the capacitance value of the capacitor and appropriately set the FV characteristic of the voltage controlled oscillator in the LC-VCO.
Japanese Patent Application Laid-Open No. 2003-78410 (Patent Document 1) and U.S. Pat. No. 7,102,446 (Patent Document 2) disclose inventions intended to appropriately set the FV characteristic. In the invention disclosed in Patent Document 1, a capacitance value of a capacitor is set in an LC-VCO so that the frequency of a first clock and the frequency of a second clock are constantly in a proportional relationship in the range of frequency variations of the first clock. In the invention disclosed in Patent Document 2, a capacitance value of a capacitor is set in an LC-VCO so that a control voltage value inputted to the LC-VCO constantly falls within a predetermined range in the range of frequency variations of the first clock.